Semiconductor device and method of manufacturing thereof

ABSTRACT

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, a stressor layer is formed in the source/drain space, a metal gate structure including part of the second semiconductor layer as channel regions is formed by a gate replacement process, after the metal gate structure is formed, the stressor layer is at least partially removed, and a source/drain contact comprising metal or a metallic material is formed in the source/drain space from which the stressor layer is at least partially removed.

RELATED APPLICATION

This application claims priority to U.S. Provisional Patent ApplicationNo. 63/166,886 filed on Mar. 26, 2021, the entire contents of which areincorporated herein by reference.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three-dimensional designs, such as amulti-gate field effect transistor (FET), including a fin FET (Fin FET)and a gate-all-around (GAA) FET. In a Fin FET, a gate electrode isadjacent to three side surfaces of a channel region with a gatedielectric layer interposed therebetween. Because the gate structuresurrounds (wraps) the fin on three surfaces, the transistor essentiallyhas three gates controlling the current through the fin or channelregion. Unfortunately, the fourth side, the bottom part of the channelis far away from the gate electrode and thus is not under close gatecontrol. In contrast, in a GAA FET, all side surfaces of the channelregion are surrounded by the gate electrode, which allows for fullerdepletion in the channel region and results in less short-channeleffects due to steeper sub-threshold current swing (SS) and smallerdrain induced barrier lowering (DIBL). As transistor dimensions arecontinually scaled down, further improvements of the GAA FET arerequired.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIGS. 1A-1D show various views of a semiconductor FET device. FIG. 1A isa cross sectional view along the X direction (source-drain direction),FIG. 1B is a cross sectional view corresponding to Y1-Y1 of FIG. 1A,FIG. 1C is a cross sectional view corresponding to Y2-Y2 of FIG. 1A andFIG. 1D shows a cross sectional view corresponding to Y3-Y3 of FIG. 1A

FIG. 1E is a cross sectional view along the source-drain direction of asemiconductor FET device according to an embodiment of the presentdisclosure.

FIGS. 2, 3, 4, 5, 6, 7 and 8 show cross sectional views of the variousstages of manufacturing a semiconductor GAA FET device according to anembodiment of the present disclosure.

FIGS. 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 and 22 showcross sectional views of the various stages of manufacturing asemiconductor GAA FET device according to an embodiment of the presentdisclosure.

FIGS. 23, 24, 25, 26, 27, 28, 29, 30, 31 and 32 show cross sectionalviews of the various stages of manufacturing a semiconductor GAA FETdevice according to an embodiment of the present disclosure.

FIGS. 33, 34, 35, 36, 37, 38, 39, 40, 41 and 42 show cross sectionalviews of the various stages of manufacturing a semiconductor GAA FETdevice according to an embodiment of the present disclosure.

FIGS. 43, 44, 45 and 46 show cross sectional views of the various stagesof manufacturing a semiconductor GAA FET device according to anembodiment of the present disclosure.

FIGS. 47, 48, 49, 50, 51, 52, 53 and 54 show cross sectional views ofthe various stages of manufacturing a semiconductor GAA FET deviceaccording to an embodiment of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“being made of” may mean either “comprising” or “consisting of” In thepresent disclosure, a phrase “one of A, B and C” means “A, B and/or C”(A, B, C, A and B, A and C, B and C, or A, B and C), and does not meanone element from A, one element from B and one element from C, unlessotherwise described.

The present disclosure is directed to a nano-scale transistor, such asgate-all-around field effect transistor (GAA FET), using a nanostructure(or nanobody), such as a nanowire or nanosheet as a channel. Inparticular, the present disclosure is directed to the formation ofstressor layers in a source/drain region and removal of the stressorlayer, to improve device performance. It is noted that in the presentdisclosure, a source and a drain are interchangeably used and thestructures thereof are substantially the same.

To improve a device performance of a GAA FET, a source/drain (S/D)epitaxial layer having a different lattice constant than the channelsemiconductor layer (channel region) is often used to apply appropriatestress to the channel region. Requirements for a process using asource/drain epitaxial layers in nanosheet GAA FETs may includeproviding sufficient stress to the channel regions; a low resistance ofthe epitaxial layer and a low contact resistance (e.g., silicideresistance); minimizing an S/D junction capacitance; and minimizingleakage by a mesa device under the channel regions. However, it isgenerally difficult to achieve these requirements at the same time.

In some embodiments of the present disclosure, a stressor layer isformed in the source/drain region before a metal gate structure isformed, and then the stressor layer is removed after the metal gatestructure is formed. The stress applied by the stressor layer to thechannel regions is substantially maintained by the metal gate structure.

In some embodiments of the present disclosure, a two-step process tore-engineer source/drain (S/D) including a pre-metal gate formationprocess and a post-metal gate formation process is provided. Thepre-metal gate formation focuses on stress tuning and eliminates theparasitic transistor under the bottommost sheet, resulting in a reducedjunction capacitance and a reduced gate-to-S/D coupling capacitance.Further, the post-metal gate formation focuses a low resistance path tochannels.

FIGS. 1A-1D show various views of a semiconductor GAA FET deviceaccording to an embodiment of the present disclosure. FIG. 1A is a crosssectional view along the X direction (source-drain direction), FIG. 1Bis a cross sectional view corresponding to Y1-Y1 of FIG. 1A, FIG. 1C isa cross sectional view corresponding to Y2-Y2 of FIG. 1A and FIG. 1Dshows a cross sectional view corresponding to Y3-Y3 of FIG. 1A. In someembodiments, the semiconductor GAA FET device of FIGS. 1A-1D is a p-typeFET.

As shown in FIGS. 1A-1C, semiconductor nanostructures 25 are providedover a semiconductor substrate 10, and vertically arranged along the Zdirection (the normal direction to the principal surface of thesubstrate 10). In some embodiments, the substrate 10 includes a singlecrystalline semiconductor layer on at least its surface portion. Thesubstrate 10 may include a single crystalline semiconductor materialsuch as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs,InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate 10is made of crystalline Si.

The substrate 10 may include in its surface region, one or more bufferlayers (not shown). The buffer layers can serve to gradually change thelattice constant from that of the substrate to that of the source/drainregions. The buffer layers may be formed from epitaxially grown singlecrystalline semiconductor materials such as, but not limited to Si, Ge,GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN,GaP, and InP. In a particular embodiment, the substrate 10 includessilicon germanium (SiGe) buffer layers epitaxially grown on the siliconsubstrate 10. The germanium concentration of the SiGe buffer layers mayincrease from 30 atomic % germanium for the bottom-most buffer layer to70 atomic % germanium for the top-most buffer layer.

As shown in FIGS. 1A-1C, the semiconductor wires or sheets (collectivelynano-structures) 25, which are channel layers, are disposed over thesubstrate 10. In some embodiments, the semiconductor nanostructures 25are disposed over a fin structure 11 (see, FIG. 3) protruding from thesubstrate 10 (a bottom fin structure 11). Each of the channel layers 25is wrapped around by a gate dielectric layer 82, and one or moreconductive layers including one or more work function adjustment layers84 and a gate electrode layer 86. The thickness T1 of the semiconductornanostructures 25 is in a range from about 5 nm to about 60 nm and thewidth W1 of the semiconductor nanostructures 25 is in a range from about5 nm to about 80 nm in some embodiments. In some embodiments, the widthof the semiconductor wires or sheets is greater than the thickness. Incertain embodiments, the width is up to twice or five times thethickness of the semiconductor nanostructures 25. In some embodiments,the semiconductor nanostructures 25 are made of Si, SiGe or Ge.

In some embodiments, an interfacial dielectric layer is formed betweenthe channel of the semiconductor nanostructure 25 and the gatedielectric layer 82. In some embodiments, the gate dielectric layer 82includes a high-k dielectric layer. The gate structure includes the gatedielectric layer 82, the gate electrode layer 84 and gate sidewallspacers 45. Although FIGS. 1A-1C show three semiconductor nanostructures25, the number of the semiconductor nanostructures 25 is not limited tothree, and may be as small as one or more than three, and may be up toten. By adjusting the number of the semiconductor wires, a drivingcurrent of the GAA FET device can be adjusted.

Further, in some embodiments, inner spacers 35 are disposed at lateralends of the gate structures and contact the gate dielectric layer 82, asshown in FIGS. 1A and 1C. The inner spacer 35 includes one or morelayers of insulating material, such as silicon oxide, silicon nitride,SiON, SiOC, SiOCN or any other suitable insulating material. In someembodiments, the inner spacer 35 includes two layers made of differentmaterial from each other.

In some embodiments, epitaxial extension layers 26 are disposed at bothlateral ends of the nanostructure 25. The epitaxial extension layers 26constitute a lightly doped drain (LDD) structure in some embodiments.The epitaxial extension layers 26 include the same semiconductormaterial as the semiconductor nanostructures 25 in some embodiments, forexample, Si, SiGe or Ge), except for a dopant condition. In someembodiments, the semiconductor nanostructures 25 are made of non-dopedsemiconductor material and the epitaxial extension layers 26 are made ofa doped semiconductor material. In other embodiments, both thesemiconductor nanostructures 25 and the epitaxial extension layers 26are doped, and the dopant concentration of the first extension layer 26is higher than the dopant concentration of the nanostructures 25(channel regions). In some embodiments, the dopant concentration of theepitaxial first extension layer 26 gradually increases from theinterface between the first extension layer 26 and the nanostructure(channel region). As shown in FIG. 1A, the first extension layer 26 onthe end face of one nanostructure 25 is separated from the firstextension layer 26 on the end face of an adjacent nanostructure 25.

In some embodiments, a silicide layer 92 is disposed on the lateral endface of the first extension layer 26 as shown in FIG. 1A. In someembodiments, the silicide layer 92 includes WSi, NiSi, TiSi or CoSi orother suitable silicide material or an alloy of a metal element andsilicon and/or germanium.

Further, as shown in FIG. 1A, a source/drain (S/D) contact 95 isdisposed to contact the silicide layers 92. In some embodiments, the S/Dcontact 95 includes one or more metal or metallic layers of Ti, TiN, Ta,TaN, Co, W, or an alloy thereof. In some embodiments, the bottom of themetal S/D contact 95 is located below the bottommost one of thenanostructures 25.

In some embodiments, a dielectric layer 49 is disposed between the S/Dcontact 95 and the bottom fin structure 11 (the substrate 10), as shownin FIGS. 1A and 1D. In some embodiments, part of the dielectric layer isdisposed as an additional inner spacer 49S between the inner spacer 35and the S/D contact 95. In some embodiments, the dielectric layer 49includes one or more layers of insulating material, such as siliconoxide, silicon nitride, SiON, SiOC, SiOCN or any other suitableinsulating materials.

An interlayer dielectric (ILD) layer 70 is disposed over the S/D contact95 and a conductive contact layer (e.g., plug or bar) 78 passing thoughthe ILD layer 70 is disposed on the S/D contact 95 in some embodiments.The conductive contact layer 95 includes one or more layers ofconductive material, such as Ti, TiN, Ta, TaN, Co, W, or an alloythereof. In some embodiments, the ILD layer 70 includes one or morelayers of insulating material, such as silicon oxide, silicon nitride,SiON, SiOC, SiOCN or any other suitable insulating materials. In someembodiments, a contact etch stop layer 68 is disposed between the ILDlayer 70 and the gate sidewall spacer 45 and on the S/D contact 95. Insome embodiments, the contact etch stop layer 68 includes one or morelayers silicon nitride, SiON, SiOC, SiOCN or any other suitableinsulating materials.

FIG. 1E is consistent with FIG. 1A, except that two metal gatestructures are illustrated in FIG. 1E, forming two GAA FETs, a first GAAFET and a second GAA FET. One of the S/D contact 95 (e.g., draincontact) is shared by the two FETs. In FIG. 1E, the semiconductornanostructures (wires or sheets) 25 (channel) are connected to metalplug via a doped epitaxial layer formed only on ends of the channels anda silicide layer. In some embodiments, no epitaxial semiconductor layermade of a different semiconductor material (e.g., SiP, SiGe, SiCP, etc.)than the channel layer 25 (e.g., Si) is formed in the source/drainspace/recess. In some embodiments, an additional inner spacer 49S madeof the same material as the dielectric layer 49 is disposed on the innerspacer 35. Although not shown in FIG. 1E, in some embodiments, the metalgate structure and the source/drain region are repeatedly arranged inthe X direction in the desired numbers depending on the designrequirements.

FIGS. 2 to 8 show various stages of manufacturing a semiconductor FETdevice according to an embodiment of the present disclosure. It isunderstood that additional operations can be provided before, during,and after processes shown by FIGS. 2-8, and some of the operationsdescribed below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable. Material, configuration, dimensions and/or processesthe same as or similar to the foregoing embodiments described withrespect to FIGS. 1A-1E may be employed in the embodiment of FIGS. 2-8,and detailed explanation thereof may be omitted. Although not shown inFIGS. 2-8, in some embodiments, the gate region and the source/drainregion are repeatedly arranged in the X direction in the desired numbersdepending on the design requirements (see, FIGS. 1A and 1E).

As shown in FIG. 2, first semiconductor layers 20 and secondsemiconductor layers 25 are alternately formed over the substrate 10.The first semiconductor layers 20 and the second semiconductor layers 25are made of materials having different lattice constants, and mayinclude one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb,InAlAs, InGaAs, GaSbP, GaAs Sb or InP.

In some embodiments, the first semiconductor layers 20 and the secondsemiconductor layers 25 are made of Si, a Si compound, SiGe, Ge or a Gecompound. In some embodiments, the first semiconductor layers 20 is madeof Si. In some embodiments, the first semiconductor layers 20 areSi_(1-x)Ge_(x), where x is equal to or more than about 0.1 and equal toor less than about 0.6, and the second semiconductor layers 25 are Si orSi_(1-y)Ge_(y), where y is smaller than x and equal to or less thanabout 0.2. In this disclosure, an “M” compound” or an “M based compound”means the majority of the compound is M.

In other embodiments, the second semiconductor layers 25 areSi_(1-x)Ge_(x), where x is equal to or more than about 0.1 and equal toor less than about 0.6, and the first semiconductor layers 20 are Si orSi_(1-y)Ge_(y), where y is smaller than x and equal to or less thanabout 0.2.

The first semiconductor layers 20 and the second semiconductor layers 25are epitaxially formed over the substrate 10 alternately. The thicknessof the first semiconductor layers 20 may be equal to or greater thanthat of the second semiconductor layers 25, and is in a range from about4 nm to about 30 nm in some embodiments, and is in a range from about 5nm to about 15 nm in other embodiments. The thickness of the secondsemiconductor layers 25 is in a range from about 4 nm to about 30 nm insome embodiments, and is in a range from about 5 nm to about 15 nm inother embodiments. The thickness of the first semiconductor layers 20may be the same as, or different from the thickness of the secondsemiconductor layers 25. Although three first semiconductor layers 20and three second semiconductor layers 25 are shown in FIG. 2, thenumbers are not limited to four, and can be 1, 2 or more than 3, and isless than 20. In some embodiments, the number of the first semiconductorlayers 20 is greater by one than the number of the second semiconductorlayers 25 (i.e. —the top layer is the first semiconductor layer).

After the stacked semiconductor layers are formed, fin structures areformed by using one or more lithography and etching operations, as shownin FIG. 3. The fin structures may be patterned by any suitable method.For example, the fin structures may be patterned using one or morephotolithography processes, including double-patterning ormulti-patterning processes. Generally, double-patterning ormulti-patterning processes combine photolithography and self-alignedprocesses, allowing patterns to be created that have, for example,pitches smaller than what is otherwise obtainable using a single, directphotolithography process. For example, in one embodiment, a sacrificiallayer is formed over a substrate and patterned using a photolithographyprocess. Spacers are formed alongside the patterned sacrificial layerusing a self-aligned process. The sacrificial layer is then removed, andthe remaining spacers may then be used to pattern the fin structures.

As shown in FIG. 3, the fin structures 29 extend in the X direction andare arranged in the Y direction. The number of the fin structures is notlimited to two as shown in FIG. 3, and may be as small as one and threeor more. In some embodiments, one or more dummy fin structures areformed on both sides of the fin structures 29 to improve patternfidelity in the patterning operations. As shown in FIG. 3, the finstructures 29 have upper portions constituted by the stackedsemiconductor layers 20, 25 and well portions 11 (a mesa structure).

The width of the upper portion of the fin structure 29 along the Ydirection is in a range from about 5 nm to about 80 nm in someembodiments, and is in a range from about 10 nm to about 40 nm in otherembodiments.

After the fin structures 29 are formed, an insulating material layerincluding one or more layers of insulating material is formed over thesubstrate so that the fin structures are fully embedded in theinsulating layer. The insulating material for the insulating layer mayinclude silicon oxide, silicon nitride, silicon oxynitride (SiON),SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectricmaterial, formed by LPCVD (low pressure chemical vapor deposition),plasma-enhanced CVD (PECVD) or flowable CVD. An anneal operation may beperformed after the formation of the insulating layer. Then, aplanarization operation, such as a chemical mechanical polishing (CMP)method and/or an etch-back method, is performed such that the uppersurface of the uppermost second semiconductor layer 25 is exposed fromthe insulating material layer. In some embodiments, one or more finliner layers are formed over the fin structures before forming theinsulating material layer. In some embodiments, the fin liner layersinclude a first fin liner layer formed over the substrate 10 andsidewalls of the bottom part of the fin structures 11, and a second finliner layer formed on the first fin liner layer. The fin liner layersare made of silicon nitride or a silicon nitride-based material (e.g.,SiON, SiCN or SiOCN). The fin liner layers may be deposited through oneor more processes such as physical vapor deposition (PVD), chemicalvapor deposition (CVD), or atomic layer deposition (ALD), although anyacceptable process may be utilized.

Then, as shown in FIG. 3, the insulating material layer is recessed toform an isolation insulating layer 15 so that the upper portions of thefin structures 29 are exposed. With this operation, the fin structures29 are separated from each other by the isolation insulating layer 15,which is also called a shallow trench isolation (STI). The isolationinsulating layer 15 may be made of suitable dielectric materials such assilicon oxide, silicon nitride, silicon oxynitride, fluorine-dopedsilicate glass (FSG), low-k dielectrics such as carbon doped oxides,extremely low-k dielectrics such as porous carbon doped silicon dioxide,a polymer such as polyimide, combinations of these, or the like. In someembodiments, the isolation insulating layer 15 is formed through aprocess such as CVD, flowable CVD (FCVD), or a spin-on-glass process,although any acceptable process may be utilized.

In some embodiments, the insulating material layer 15 is recessed untilthe upper portion of the fin structure (well layer) 11 is exposed. Inother embodiments, the upper portion of the fin structure 11 is notexposed. The first semiconductor layers 20 are sacrificial layers whichare subsequently partially removed, and the second semiconductor layers25 are subsequently formed into semiconductor wires or sheets as channellayers of a GAA FET. In other embodiments, the second semiconductorlayers 25 are sacrificial layers which are subsequently partiallyremoved, and the first semiconductor layers 20 are subsequently formedinto semiconductor wires or sheets as channel layers.

After the isolation insulating layer 15 is formed, a sacrificial (dummy)gate structure 40 is formed, as shown in FIG. 4. FIG. 4 illustrates astructure after a sacrificial gate structure 40 is formed over theexposed fin structures 29. The sacrificial gate structure 40 is formedover a portion of the fin structures which is to be a channel region.The sacrificial gate structure 40 defines the channel region of the GAAFET. The sacrificial gate structure 40 includes a sacrificial gatedielectric layer 41 and a sacrificial gate electrode layer 42. Thesacrificial gate dielectric layer 41 includes one or more layers ofinsulating material, such as a silicon oxide-based material. In oneembodiment, silicon oxide formed by CVD is used. The thickness of thesacrificial gate dielectric layer 41 is in a range from about 1 nm toabout 5 nm in some embodiments.

The sacrificial gate structure 40 is formed by first blanket depositingthe sacrificial gate dielectric layer 41 over the fin structures. Asacrificial gate electrode layer is then blanket deposited on thesacrificial gate dielectric layer and over the fin structures, such thatthe fin structures are fully embedded in the sacrificial gate electrodelayer. The sacrificial gate electrode layer includes silicon such aspolycrystalline silicon or amorphous silicon. The thickness of thesacrificial gate electrode layer is in a range from about 100 nm toabout 200 nm in some embodiments. In some embodiments, the sacrificialgate electrode layer is subjected to a planarization operation. Thesacrificial gate dielectric layer and the sacrificial gate electrodelayer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, orother suitable process. Subsequently, a mask layer is formed over thesacrificial gate electrode layer. The mask layer includes a pad siliconnitride layer 43 and a silicon oxide mask layer 44.

Next, a patterning operation is performed on the mask layer andsacrificial gate electrode layer is patterned into the sacrificial gatestructure 40, as shown in FIG. 4. The sacrificial gate structureincludes the sacrificial gate dielectric layer 41, the sacrificial gateelectrode layer 42 (e.g., poly silicon), the pad silicon nitride layer43 and the silicon oxide mask layer 44. By patterning the sacrificialgate structure, the stacked layers of the first and second semiconductorlayers are partially exposed on opposite sides of the sacrificial gatestructure, thereby defining source/drain regions, as shown in FIG. 4. Inthis disclosure, a source and a drain are interchangeably used and thestructures thereof are substantially the same. In some embodiments, onesacrificial gate structure is formed over one or more fin structures,but the number of the sacrificial gate structures per fin structure isnot limited to one. Two or more sacrificial gate structures are arrangedin the X direction in some embodiments. In certain embodiments, one ormore dummy sacrificial gate structures are formed on both sides of thesacrificial gate structures to improve pattern fidelity.

Further, a first cover layer 45 for gate sidewall spacers is formed overthe sacrificial gate structure 40, as shown in FIG. 4. The first coverlayer 45 is deposited in a conformal manner so that it is formed to havesubstantially equal thicknesses on vertical surfaces, such as thesidewalls, horizontal surfaces, and the top of the sacrificial gatestructure, respectively. In some embodiments, the first cover layer 45has a thickness in a range from about 5 nm to about 20 nm. The firstcover layer 45 includes one or more of silicon nitride, SiON, SiCN,SiCO, SiOCN or any other suitable dielectric material. The cover layer45 can be formed by ALD or CVD, or any other suitable method.

Next, as shown in FIG. 5, the first cover layer 45 is anisotropicalyetched to remove the first cover layer 45 disposed on the source/drainregion, while leaving the first cover layer 45 as sidewall spacers onside faces of the sacrificial gate structure 40. FIG. 5 shows a crosssectional view along the X direction. Then the stacked structure of thefirst semiconductor layers 20 and the second semiconductor layer 25 isetched down at the source/drain region, by using one or more lithographyand etching operations, thereby forming a source/drain space 21. In someembodiments, the substrate 10 (or the bottom part of the fin structures11) is also partially etched to form a mesa structure. In someembodiments, an n-type FET and a p-type FET are manufactured separately,and in such a case, a region for one type of FET is processed, and aregion for the other type of FET is covered by a protective layer, suchas a silicon nitride. In some embodiments, as shown in FIG. 5, therecessed fin structure has a U-shape. In other embodiments, the recessedfin structure has a V-shape showing (111) facets of silicon crystal. Inother embodiments, the recess has a reverse trapezoid shape, or arectangular shape.

In some embodiments, the recess is formed by a dry etching process,which may be anisotropic. The anisotropic etching process may beperformed using a process gas mixture including BF₂, Cl₂, CH₃F, CH₄,HBr, O₂, Ar, other etchant gases. Process gases may be activated into aplasma by any suitable method of generating the plasma, such astransformer coupled plasma (TCP) systems, inductively coupled plasma(ICP) systems, magnetically enhanced reactive ion techniques. The plasmais a remote plasma that is generated in a separate plasma generationchamber connected to the processing chamber in some embodiments. Theprocess gases used in the plasma etching process includes etchant gasessuch as H₂, Ar, other gases, or a combination of gases. In someembodiments, carrier gases, such as N₂, Ar, He, Xe, are combined withthe a plasma etching process gas using hydrogen (H) radicals. The Hradicals may be formed by flowing H₂ gas into a plasma generationchamber and igniting a plasma within the plasma generation chamber. Insome embodiments, an additional gas may be ignited into a plasma withinthe plasma generation chamber, such as Ar. The H radicals mayselectively etch (100) planes over (111) planes or (110) planes. In somecases, the etch rate of the (100) planes is be about three times greaterthan the etch rate of (111) planes. Due to this selectivity, the etchingby the H radicals may tend to slow or stop along (111) planes or (110)planes of silicon during the second patterning process.

Further, as shown in FIG. 6, the first semiconductor layers 20 arelaterally etched in the X direction within the source/drain space 21,thereby forming cavities 22. When the first semiconductor layers 20 areSiGe and the second semiconductor layers 25 are Si, the firstsemiconductor layers 20 can be selectively etched by using a wet etchantsuch as, but not limited to, a mixed solution of H₂O₂, CH₃COOH and HF,followed by H₂O cleaning. In some embodiments, the etching by the mixedsolution and cleaning by water is repeated 10 to 20 times. The etchingtime by the mixed solution is in a range from about 1 min to about 2 minin some embodiments. The mixed solution is used at a temperature in arange from about 60° C. to about 90° C. in some embodiments. In someembodiments, other etchants are used.

In some embodiments, the cavity 22 has a curved end shape convex towardthe first semiconductor layer 20 (lateral U-shape cross section). Inother embodiments, the cavity 22 has a lateral V-shape cross sectionhaving apex at the first semiconductor layer 20.

Next, as shown in FIG. 7, a first insulating layer 30 is formed on theetched lateral ends of the first semiconductor layers 20 and on endfaces of the second semiconductor layers 25 in the source/drain space 21and over the sacrificial gate structure 40. In some embodiments, thefirst insulating layer 30 fills the source/drain space 21 as shown inFIG. 7, and in other embodiments, the first insulating layer 30 isconformally formed so that a space is left in the source/drain space 21.The first insulating layer 30 includes one of silicon nitride andsilicon oxide, SiON, SiOC, SiCN and SiOCN, or any other suitabledielectric material. The first insulating layer 30 is made of adifferent material than the sidewall spacers (first cover layer) 45 insome embodiments, and is made of the same material as the sidewallspacers 45 in other embodiments. The first insulating layer 30 can beformed by ALD or any other suitable methods. By forming the firstinsulating layer 30, the cavities 22 are fully filled with the firstinsulating layer 30.

After the first insulating layer 30 is formed, an etching operation isperformed to partially remove the first insulating layer 30, therebyforming inner spacers 35, as shown in FIG. 8. In some embodiments, theend face of the inner spacers 35 is recessed more than the end face ofthe second semiconductor layers 25. The recessed amount is in a rangefrom about 0.2 nm to about 3 nm and is in a range from about 0.5 nm toabout 2 nm in other embodiments. In other embodiments, the recessedamount is less than 0.5 nm and may be equal to zero (i.e. —the end faceof the inner spacer 35 and the end face of the second semiconductorlayers 25 are flush with each other).

In some embodiments, before forming the first insulating layer 30, anadditional insulating layer having a smaller thickness than the firstinsulating layer 30 is formed, and thus the inner spacers 35 have atwo-layer structure. In some embodiments, widths (lateral length) of theinner spacers 35 are not constant.

FIGS. 9-22 show various stages of manufacturing a semiconductor FETdevice according to an embodiment of the present disclosure. It isunderstood that additional operations can be provided before, during,and after processes shown by FIGS. 9-22, and some of the operationsdescribed below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable. Material, configuration, dimensions and/or processesthe same as or similar to the foregoing embodiments described withrespect to FIGS. 1A-1E and 2-8 may be employed in the embodiment ofFIGS. 9-22, and detailed explanation thereof may be omitted. Althoughnot shown in FIGS. 9-22, in some embodiments, the gate region and thesource/drain region are repeatedly arranged in the X direction in thedesired numbers depending on the design requirements (see, FIGS. 1A and1E).

FIG. 9 is consistent with FIG. 8 except that some of the features areomitted for simplicity. After the inner spacers 35 are formed, anepitaxial first extension layer 26 is formed on lateral end faces of thesecond semiconductor layer 25 in some embodiments, as shown in FIG. 10.In some embodiments, the first extension layer 26 includes Si doped withP or As for an n-type FET and B for a p-type FET. In some embodiments,the dopant concentration of the first extension layer 26 is higher thanthe dopant concentration of the second semiconductor layers 25. In someembodiments, the dopant concentration of the epitaxial first extensionlayer 26 gradually increases from the interface between the firstextension layer 26 and the second semiconductor layers 25 to thesource/drain space 21. In some embodiments, the thickness of the firstextension layer 26 as deposited is in a range from about 1 nm to about10 nm. In some embodiments, during the epitaxial formation of the firstextension layer 26, some of the dopant elements diffuse into the secondsemiconductor layer 25 to a depth of about 0.5 nm to about 2 nm.

Then, as shown in FIG. 11, an epitaxial stressor layer 50 is formed inthe source/drain space 21. In some embodiments, the epitaxial stressorlayer 50 include one or more layers of SiC, SiP, SiAs and/or SiCP for ann-type FET. In certain embodiments, SiC or SiCP is used. In someembodiments, the epitaxial stressor layer 50 includes SiGe, SiGeSn Ge,GeSn and/or SiSn for a p-type FET. When SiGe is used, the Ge content isabout 60 atomic % to about 80 atomic % in some embodiments. Theepitaxial stressor layer 50 applies a tensile stress to the secondsemiconductor layer 25 for an n-type FET and a compressive stress to thep-type FET.

Then, a dielectric layer 70A is formed over the epitaxial stressor layer50 and the dummy gate structure as shown in FIG. 12. In someembodiments, before the dielectric layer 70A is formed, a contact etchstop layer (see, layer 68 shown in FIG. 1A) is formed.

Next, the dielectric layer 70A is planarized by CMP to expose the dummygate electrode layer 42, and then the dummy gate electrode layer 42 andthe sacrificial gate dielectric layer 41 are removed. The dielectriclayer 70A protects the epitaxial stressor layers 50 during the removalof the sacrificial gate structures. The sacrificial gate structures canbe removed using plasma dry etching and/or wet etching. When thesacrificial gate electrode layer 42 is polysilicon and the dielectriclayer 70A is silicon oxide, a wet etchant such as a TMAH solution can beused to selectively remove the sacrificial gate electrode layer 42. Thesacrificial gate dielectric layer 41 is thereafter removed using plasmadry etching and/or wet etching. The materials for the dielectric layer70A include compounds comprising Si, O, C and/or H, such as siliconoxide, SiCOH and SiOC. Organic materials, such as polymers, may be usedfor the dielectric layer 70A.

After the sacrificial gate structures are removed, the firstsemiconductor layers 20 are removed, thereby forming wires or sheets(channel regions) of the second semiconductor layers 25 as shown in FIG.13. The first semiconductor layers 20 can be removed or etched using anetchant that can selectively etch the first semiconductor layers 20against the second semiconductor layers 25, as set forth above. Sincethe first insulating layers (inner spacers) 35 are formed, the etchingof the first semiconductor layers 20 stops at the first insulating layer35. In other words, the first insulating layer 35 functions as anetch-stop layer for etching of the first semiconductor layers 20.

After the semiconductor wires or sheets (channel regions) of the secondsemiconductor layers 25 are formed, a metal gate structure is formed asshown in FIG. 14. In some embodiments, the structure and/or material ofthe gate electrode for the n-type GAA FET are different from thestructure and/or material of the gate electrode for the p-type GAA FET.

In certain embodiments, the gate dielectric layer 82 includes one ormore layers of a dielectric material, such as silicon oxide, siliconnitride, or high-k dielectric material, other suitable dielectricmaterial, and/or combinations thereof. Examples of high-k dielectricmaterial include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconiumoxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina(HfO₂—Al₂O₃) alloy, other suitable high-k dielectric materials, and/orcombinations thereof. In some embodiments, the gate dielectric layer 82includes an interfacial layer (not shown) formed between the channellayers and the dielectric material.

The gate dielectric layer 82 may be formed by CVD, ALD or any suitablemethod. In one embodiment, the gate dielectric layer is formed using ahighly conformal deposition process such as ALD in order to ensure theformation of a gate dielectric layer having a uniform thickness aroundeach channel layer. The thickness of the gate dielectric layer 82 is ina range from about 1 nm to about 6 nm in one embodiment.

In some embodiments, the metal gate structure includes one or more workfunction adjustment layers 84 disposed over the gate dielectric layer82. The work function adjustment layers 84 are made of a conductivematerial such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al,TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of thesematerials. In some embodiments, one or more of TiAlC, Al, TiAl, TaN,TaAlC, TiN, TiC and Co are used as the work function adjustment layerfor the p-channel FET. For an n-channel FET, one or more of TaN, TaAlC,TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work functionadjustment layer. The work function adjustment layer may be formed byALD, PVD, CVD, e-beam evaporation, or other suitable process. Further,the work function adjustment layer may be formed separately for then-channel FET and the p-channel FET which may use different metallayers.

The gate electrode layer 86 is formed on the work function adjustmentlayer 84 to surround each channel layer. The gate electrode layer 86includes one or more layers of conductive material, such as polysilicon,aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum,tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl,TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/orcombinations thereof.

The gate electrode layer 86 may be formed by CVD, ALD, electro-plating,or other suitable method. The gate electrode layer is also depositedover the upper surface of the dielectric layer 70A. The gate dielectriclayer and the gate electrode layer formed over the dielectric layer 70Aare then planarized by using, for example, CMP, until the top surface ofthe dielectric layer 70A is revealed. In some embodiments, after theplanarization operation, the gate electrode layer is recessed and a capinsulating layer (not shown) is formed over the recessed gate electrode.The cap insulating layer includes one or more layers of a siliconnitride-based material, such as silicon nitride. The cap insulatinglayer is formed by depositing an insulating material followed by aplanarization operation.

By forming the metal gate structure around the second semiconductorlayers 25, the stress imposed by the epitaxial stressor layer 50 is heldand maintained by the metal gate structure.

Subsequently, an additional dielectric layer 70B is formed over thedielectric layer 70A and the metal gate structure as shown in FIG. 15.The materials for the additional dielectric layer 70B include compoundscomprising Si, 0, C and/or H, such as silicon oxide, SiCOH and SiOC.Organic materials, such as polymers, may be used for the dielectriclayer 70B. In some embodiments, the materials of the dielectric layers70A and 70B are the same. After FIG. 15, the combination of thedielectric layers 70A and 70B is referred to as an ILD layer 70.

Then, an opening 71 is formed in the ILD layer 70 by using one or morelithography and etching operations to expose an upper surface of theepitaxial stressor layer, as shown in FIG. 16.

Next, the stressor layer 50 is selectively removed through the opening71, thereby reforming a source/drain space 21′, as shown in FIG. 17.Since the composition of the epitaxial semiconductor stressor layer 50is sufficiently different from the composition of the extensionsemiconductor layer 26 and the substrate 10, the stressor layer 50 canbe removed by dry and/or wet etching selective to the first extensionlayer 26 and the substrate 10. As set forth above, even after thestressor layer 50 is removed, the stress imposed by the epitaxialstressor layer 50 is held and maintained by the metal gate structure.

Further, as shown in FIG. 18, a dielectric layer 49L is formed to fillthe source/drain space 21′. In some embodiments, the dielectric layer49L includes one or more layers of silicon nitride, SiON, SiCN, SiCO,SiOCN or any other suitable dielectric material. The dielectric layer49L can be formed by ALD or CVD, or any other suitable method.

Then, the dielectric layer 49L is partially removed by one or more ofisotropic and anisotropic etching, thereby forming the dielectric layer49, as shown in FIG. 19. The remaining thickness of the dielectric layer49 is in a range from about 2 nm to about 20 nm in some embodiments atthe bottom of the source/drain space 21′. The dielectric layer 49suppress a leak current between the source and the drain through themesa structure 11. As shown in FIG. 19, part of the dielectric layer 49remains on the inner spacer 35 as an additional inner spacer 49S.

After the dielectric layer 49 is formed, a second extensionsemiconductor layer 90 is formed on the first extension layer 26 asshown in FIG. 20. In some embodiments, the second extension layer 90includes doped Si. The second extension semiconductor layer 90 isselectively formed on the first extension layer 26 in a self-aligningmanner.

In some embodiments, the second extension layer 90 includes Si dopedwith P or As for an n-type FET and B for a p-type FET. In someembodiments, the thickness of the second extension layer 90 as depositedis in a range from about 1 nm to about 10 nm. In some embodiments, thesecond extension layer 90 is formed by ALD or CVD at a temperature about250° C. to 350° C., which is lower than the formation temperatures ofthe first extension layer 26 and the stressor layer 50.

Then, an alloy layer (e.g., silicide layer) 92 is formed on the secondextension layer 90, as shown in FIG. 21. In some embodiments, a metallayer is formed on the second extension layer 90 and a thermal operationis performed to react the metal material and the semiconductor materialof the second extension layer 90 to form the alloy layer 92. Thus, allof or a part of the second extension layer 90 is consumed into the alloylayer 92. In some embodiments, the silicide layer 92 includes one ormore of WSi, CoSi, NiSi, TiSi, MoSi and TaSi.

Further, one or more conductive layers are formed in the source/drainspace 21′ to form a source/drain (S/D) contact 95 as shown in FIG. 22.In some embodiments, the S/D contact 95 includes one or more layers ofCo, Ni, W, Ti, Ta, Cu, Al, TiN and TaN.

It is understood that the GAA FETs undergo further CMOS processes toform various features such as contacts/vias, interconnect metal layers,dielectric layers, passivation layers, etc.

FIGS. 23-32 show various stages of manufacturing a semiconductor FETdevice according to an embodiment of the present disclosure. It isunderstood that additional operations can be provided before, during,and after processes shown by FIGS. 23-32, and some of the operationsdescribed below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable. Material, configuration, dimensions and/or processesthe same as or similar to the foregoing embodiments described withrespect to FIGS. 1A-1E, 2-8 and 9-22 may be employed in the embodimentof FIGS. 23-32, and detailed explanation thereof may be omitted.Although not shown in FIGS. 22-32, in some embodiments, the gate regionand the source/drain region are repeatedly arranged in the X directionin the desired numbers depending on the design requirements (see, FIGS.1A and 1E).

After the structure shown in FIG. 10 is formed, a dielectric stressorlayer 55 is formed in the source/drain space 21. In some embodiments,the dielectric stressor layer 55 includes one or more layers ofdielectric materials. In some embodiments, as shown in FIG. 23, a firstdielectric stressor layer 52 and a second dielectric stressor layer 54having an internal stress different from the first dielectric layer 52are formed in the source/drain space 21.

For an n-type FET, a tensile stress is applied to the secondsemiconductor layers 25 by the dielectric stressor layers. In someembodiments, the second dielectric stressor layer 54 has a highertensile stress than the first dielectric stressor layer 52. In otherembodiments, the second dielectric stressor layer 54 has a lower tensilestress than the first dielectric stressor layer 52. For a p-type FET, acompressive stress is applied to the second semiconductor layers 25 bythe dielectric stressor layers. In some embodiments, the seconddielectric stressor layer 54 has a higher compressive stress than thefirst dielectric stressor layer 52. In some embodiments, the seconddielectric stressor layer 54 has a lower compressive stress than thefirst dielectric stressor layer 52.

The stress directions (tensile or compressive) and the amount of stresscan be adjusted by adjusting one or more parameters in a film formationmethod. In some embodiments, the first and second dielectric stressorlayers 52 and 54 are made of silicon nitride formed from SiH₄ (and/orSi₂H₆) and NH₃, i.e., hydrogenated silicon nitride (SiN:H), using plasmaor thermal CVD methods. In other embodiments, after a silicon nitridefilm is formed, an ion implantation process is performed to introduceions of one or more of Si, N, O, Ge, Ar or He. The stress properties ofthe hydrogenated silicon nitride film depend on the amount of hydrogenin the film, an amount of impurities and/or a thickness of the film. Byadjusting one or more parameters of the film formation process, theamount of hydrogen contained in the hydrogenated silicon nitride filmcan be adjusted. In some embodiments, a tensile stress silicon nitridefilm can be manufactured by LPCVD or PECVD process. In some embodiments,the use of LPCVD can create a high-tensile-stress Si₃N₄ films up to 2Gpa. When PECVD is used the tensile stress may be about 1 GPa.

In some embodiments, the first dielectric stressor layer 52 isconformally formed in the source/drain space 21 and the seconddielectric stressor layer 54 is formed to fully fill the source/drainspace 21. In some embodiments, a thickness of the first dielectricstressor layer 52 is in a range from about 1 nm to about 5 nm.

Then, similar to FIG. 12, a dielectric layer 70A is formed over theepitaxial stressor layer 50 and the dummy gate structure as shown inFIG. 24.

Next, similar to FIG. 13, the dummy gate electrode layer 42 and thesacrificial gate dielectric layer 41 are removed, and the firstsemiconductor layers 20 are removed, thereby forming wires or sheets(channel regions) of the second semiconductor layers 25 as shown in FIG.25. After the semiconductor wires or sheets (channel regions) of thesecond semiconductor layers 25 are formed, similar to FIG. 14, a metalgate structure is formed as shown in FIG. 26.

Subsequently, similar to FIG. 15, an additional dielectric layer 70B isformed over the dielectric layer 70A and the metal gate structure, asshown in FIG. 27. Then, similar to FIG. 16, an opening 71 is formed inthe ILD layer 70 by using one or more lithography and etching operationsto expose an upper surface of the epitaxial stressor layer, as shown inFIG. 28.

Next, the second dielectric stressor layer 54 is selectively removedthrough the opening 71, thereby reforming a source/drain space 21′, asshown in FIG. 29. Since the internal stress of the second dielectricstressor layer 54 is sufficiently different from the internal stress ofthe first dielectric stressor layer 52, the second dielectric stressorlayer 54 can be removed by dry and/or wet etching selective to the firstdielectric stressor layer 52. As set forth above, even after the seconddielectric stressor layer 54 is removed, the stress imposed by thesecond dielectric stressor layer 54 is held and maintained by the metalgate structure.

After the second dielectric stressor layer 54 is removed, similar toFIG. 20, a second extension semiconductor layer 90 is formed on thefirst extension layer 26, as shown in FIG. 30. Then, similar to FIG. 21,an alloy layer (e.g., silicide layer) 92 is formed on the secondextension layer 90, as shown in FIG. 31. Further, similar to FIG. 22,one or more conductive layers are formed in the source/drain space 21′to form a source/drain (S/D) contact 95 as shown in FIG. 32. It isunderstood that the GAA FETs undergo further CMOS processes to formvarious features such as contacts/vias, interconnect metal layers,dielectric layers, passivation layers, etc.

FIGS. 33-46 show various stages of manufacturing a semiconductor FETdevice according to an embodiment of the present disclosure. It isunderstood that additional operations can be provided before, during,and after processes shown by FIGS. 33-46, and some of the operationsdescribed below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable. Material, configuration, dimensions and/or processesthe same as or similar to the foregoing embodiments described withrespect to FIGS. 1A-1E, 2-8 and 9-32 may be employed in the embodimentof FIGS. 33-46, and detailed explanation thereof may be omitted.Although not shown in FIGS. 33-46, in some embodiments, the gate regionand the source/drain region are repeatedly arranged in the X directionin the desired numbers depending on the design requirements (see, FIGS.1A and 1E).

In some embodiments, when forming the inner spacers 35, a bottom of thefirst insulating layer 30 formed in the source/drain space 21 as shownin FIG. 7 is not fully removed and a part thereof remains as a remainingfirst insulating layer 34 as shown in FIG. 33. In some embodiments, theupper surface of the remaining first insulating layer 34 is locatedbelow the lower surface of the bottommost second semiconductor layer 25.In some embodiments, the upper surface of the remaining first insulatinglayer 34 is located above the lower surface of the bottommost firstsemiconductor layer 20. In other embodiments, the upper surface of theremaining first insulating layer 34 is located below the lower surfaceof the bottommost first semiconductor layer 20.

After the inner spacers 35 and the remaining first insulating layer 34are formed, similar to FIG. 10, an epitaxial first extension layer 26 isformed on lateral end faces of the second semiconductor layer 25 in someembodiments, as shown in FIG. 34.

Subsequently, a dielectric stressor layer 56 is formed in thesource/drain space 21 as shown in FIG. 35. In some embodiments, thedielectric stressor layer 55 includes one or more layers of dielectricmaterials. For an n-type FET, a tensile stress is applied to the secondsemiconductor layers 25 by the dielectric stressor layer 56. For ap-type FET, a compressive stress is applied to the second semiconductorlayers 25 by the dielectric stressor layer 56. In some embodiments, thedielectric stressor layer 56 is made of silicon nitride formed from SiH₄(and/or Si₂H₆) and NH₃, i.e., hydrogenated silicon nitride (SiN:H),using plasma or thermal CVD methods. In other embodiments, after asilicon nitride film is formed, an ion implantation process is performedto introduce ions of one or more of Si, N, O, Ge, Ar or He. The stressproperties of the hydrogenated silicon nitride film depend on the amountof hydrogen in the film, an amount of impurities and/or a thickness ofthe film. By adjusting one or more parameters of the film formationprocess, the amount of hydrogen contained in the hydrogenated siliconnitride film can be adjusted. In some embodiments, the dielectricstressor layer 56 is made of a different material than the firstinsulating layer 34.

Then, similar to FIGS. 12 and 24, a dielectric layer 70A is formed overthe epitaxial stressor layer 50 and the dummy gate structure as shown inFIG. 36.

Next, similar to FIGS. 13-15 and 25-27, the dummy gate electrode layer42 and the sacrificial gate dielectric layer 41 are removed, and thefirst semiconductor layers 20 are removed, thereby forming wires orsheets (channel regions) of the second semiconductor layers 25. Afterthe semiconductor wires or sheets (channel regions) of the secondsemiconductor layers 25 are formed, a metal gate structure is formed,and subsequently, an additional dielectric layer 70B is formed over thedielectric layer 70A and the metal gate structure, as shown in FIG. 37.Then, similar to FIGS. 16 and 28, an opening 71 is formed in the ILDlayer 70 by using one or more lithography and etching operations toexpose an upper surface of the epitaxial stressor layer, as shown inFIG. 38.

Next, the dielectric stressor layer 56 is selectively removed throughthe opening 71, thereby reforming a source/drain space 21′, as shown inFIG. 39. Since the internal stress of the dielectric stressor layer 56is sufficiently different from the internal stress of the remainingfirst insulating layer 34, the dielectric stressor layer 56 can beremoved by dry and/or wet etching selective to the remaining firstinsulating layer 34. As set forth above, even after the dielectricstressor layer 56 is removed, the stress imposed by the dielectricstressor layer 56 is held and maintained by the metal gate structure. Asshown in FIG. 39, a part of the dielectric stressor layer 56 remains onthe inner spacer 35 as an additional inner spacer 56S.

After the dielectric stressor layer 56 is removed, similar to FIGS. 20and 30, a second extension semiconductor layer 90 is formed on the firstextension layer 26, as shown in FIG. 40. Then, similar to FIGS. 21 and31, an alloy layer (e.g., silicide layer) 92 is formed on the secondextension layer 90, as shown in FIG. 41. Further, similar to FIGS. 22and 32, one or more conductive layers are formed in the source/drainspace 21′ to form a source/drain (S/D) contact 95 as shown in FIG. 42.It is understood that the GAA FETs undergo further CMOS processes toform various features such as contacts/vias, interconnect metal layers,dielectric layers, passivation layers, etc.

In some embodiments, as shown in FIG. 43, the dielectric stressor layer56 includes a first dielectric stressor layer 56A and a seconddielectric stressor layer 56B similar to the first dielectric stressorlayer 52 and the second dielectric stressor layer 54 as set forth above.

For an n-type FET, a tensile stress is applied to the secondsemiconductor layers 25 by the dielectric stressor layers. In someembodiments, the second dielectric stressor layer 56B has a highertensile stress than the first dielectric stressor layer 56A. In otherembodiments, the second dielectric stressor layer 56B has a lowertensile stress than the first dielectric stressor layer 56A. For ap-type FET, a compressive stress is applied to the second semiconductorlayers 25 by the dielectric stressor layers. In some embodiments, thesecond dielectric stressor layer 56B has a higher compressive stressthan the first dielectric stressor layer 56A. In some embodiments, thesecond dielectric stressor layer 56B has a lower compressive stress thanthe first dielectric stressor layer 56A.

The stress directions (tensile or compressive) and the amount of stresscan be adjusted by adjusting one or more parameters in a film formationmethod. In some embodiments, the first and second dielectric stressorlayers 56A and 56B are made of silicon nitride formed from SiH₄ (and/orSi₂H₆) and NH₃, i.e., hydrogenated silicon nitride (SiN:H), using plasmaor thermal CVD methods. In other embodiments, after a silicon nitridefilm is formed, an ion implantation process is performed to introduceions of one or more of Si, N, O, Ge, Ar or He. The stress properties ofthe hydrogenated silicon nitride film depend on the amount of hydrogenin the film, an amount of impurities and/or a thickness of the film. Byadjusting one or more parameters of the film formation process, theamount of hydrogen contained in the hydrogenated silicon nitride filmcan be adjusted.

In some embodiments, after the first dielectric stressor layer 56A isconformally formed, one or more anisotropic etching operations areperformed to expose a part of the remaining first insulating layer 34,and then the second dielectric stressor layer 56B is formed, as shown inFIG. 43. In other embodiments, the second dielectric stressor layer 56Bis sequentially formed on the first dielectric stressor layer 56A andthus the second dielectric stressor layer 56B is not in direct contactwith the remaining first insulating layer 34.

Next, similar to FIGS. 13-15 and 25-27, the dummy gate electrode layer42 and the sacrificial gate dielectric layer 41 are removed, and thefirst semiconductor layers 20 are removed, thereby forming wires orsheets (channel regions) of the second semiconductor layers 25. Afterthe semiconductor wires or sheets (channel regions) of the secondsemiconductor layers 25 are formed, a metal gate structure is formed,and subsequently, an additional dielectric layer 70B is formed over thedielectric layer 70A and the metal gate structure, as shown in FIG. 44.

Then, similar to FIGS. 16 and 28, an opening 71 is formed in the ILDlayer 70 by using one or more lithography and etching operations toexpose an upper surface of the epitaxial stressor layer. Next, thesecond dielectric stressor layer 56B is selectively removed through theopening 71, thereby reforming a source/drain space 21′, as shown in FIG.45. Since the internal stress of the second dielectric stressor layer56B is sufficiently different from the internal stress of the firstdielectric stressor layer 56A and the remaining first insulating layer34, the second dielectric stressor layer 56N can be removed by dryand/or wet etching selective to the first dielectric stressor layer 56Aand the remaining first insulating layer 34. As set forth above, evenafter the second dielectric stressor layer 56B is removed, the stressimposed by the dielectric stressor layer 56B is held and maintained bythe metal gate structure.

After the dielectric stressor layer 56 is removed, similar to FIGS.20-22 and 30-32, a second extension semiconductor layer 90 is formed onthe first extension layer 26, an alloy layer (e.g., silicide layer) 92is formed on the second extension layer 90, and one or more conductivelayers are formed in the source/drain space 21′ to form a source/drain(S/D) contact 95 as shown in FIG. 46. It is understood that the GAA FETsundergo further CMOS processes to form various features such ascontacts/vias, interconnect metal layers, dielectric layers, passivationlayers, etc.

FIGS. 47-54 show various stages of manufacturing a semiconductor FETdevice according to an embodiment of the present disclosure. It isunderstood that additional operations can be provided before, during,and after processes shown by FIGS. 47-54, and some of the operationsdescribed below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable. Material, configuration, dimensions and/or processesthe same as or similar to the foregoing embodiments described withrespect to FIGS. 1A-1E, 2-8 and 9-46 may be employed in the embodimentof FIGS. 47-54, and detailed explanation thereof may be omitted.

FIG. 47 is consistent with FIG. 7. In some embodiments, the firstinsulating layer 30 has a tensile or compressive internal stress toapply stress to the second semiconductor layers 25. For an n-type FET, atensile stress is applied to the second semiconductor layers 25 by thefirst insulating layer 30. For a p-type FET, a compressive stress isapplied to the second semiconductor layers 25 by the first insulatinglayer 30. In some embodiments, the first insulating layer 30 includestwo or more layers, similar to the first and second dielectric stressorlayers 52 and 54 as set forth above.

The stress directions (tensile or compressive) and the amount of stresscan be adjusted by adjusting one or more parameters in a film formationmethod. In some embodiments, first insulating layer 30 is made ofsilicon nitride formed from SiH₄ (and/or Si₂H₆) and NH₃, i.e.,hydrogenated silicon nitride (SiN:H), using plasma or thermal CVDmethods. In other embodiments, after a silicon nitride film is formed,an ion implantation process is performed to introduce ions of one ormore of Si, N, O, Ge, Ar or He. The stress properties of thehydrogenated silicon nitride film depend on the amount of hydrogen inthe film, an amount of impurities and/or a thickness of the film. Byadjusting one or more parameters of the film formation process, theamount of hydrogen contained in the hydrogenated silicon nitride filmcan be adjusted.

Then, similar to FIG. 12, a dielectric layer 70A is formed over theepitaxial stressor layer 50 and the dummy gate structure as shown inFIG. 48.

Next, similar to FIG. 13, the dummy gate electrode layer 42 and thesacrificial gate dielectric layer 41 are removed, and the firstsemiconductor layers 20 are removed, thereby forming wires or sheets(channel regions) of the second semiconductor layers 25. After thesemiconductor wires or sheets (channel regions) of the secondsemiconductor layers 25 are formed, similar to FIG. 14, a metal gatestructure is formed. Subsequently, similar to FIG. 15, an additionaldielectric layer 70B is formed over the dielectric layer 70A and themetal gate structure, as shown in FIG. 49. Then, similar to FIG. 16, anopening 71 is formed in the ILD layer 70 by using one or morelithography and etching operations to expose an upper surface of theepitaxial stressor layer, as shown in FIG. 50.

Next, a part of the first insulating layer 30 is removed through theopening 71, thereby reforming a source/drain space 21′, as shown in FIG.51. The thickness at the bottom of the source/drain space 21′ of thefirst insulating layer 30 is in a range from about 1 nm to about 5 nm insome embodiments. The inner spacers 35 are also formed at the same time.

After the first insulating layer 30 is partially removed and the innerspacers 35 are formed, similar to FIG. 20, a second extensionsemiconductor layer 90 is formed on the end faces of the secondsemiconductor layers 25, as shown in FIG. 52. In some embodiments,before the second extension semiconductor layer 90 is formed, a firstextension layer 26 is formed on the end faces of the secondsemiconductor layers 25. Then, similar to FIG. 21, an alloy layer (e.g.,silicide layer) 92 is formed on the second extension layer 90, as shownin FIG. 53. Further, similar to FIG. 22, one or more conductive layersare formed in the source/drain space 21′ to form a source/drain (S/D)contact 95 as shown in FIG. 54. It is understood that the GAA FETsundergo further CMOS processes to form various features such ascontacts/vias, interconnect metal layers, dielectric layers, passivationlayers, etc.

In the present disclosure, the source/drain region of the GAA FET doesnot include an epitaxial stressor layer, for example, SiP, SiCP and/orSiC for an n-type FET and SiGe for a p-type FET, but the channel layers25 experiences and maintains the stress applied by the epitaxialstressor layer 50. Further, since no epitaxial stressor layer (havinggenerally higher resistance than the metal or metallic material) existsand the metal or metallic S/D contact 95 directly contacts thesource/drain regions of the channel layers 25, it is possible to reduceresistance at the source/drain region. In addition, since the bottom ofthe S/D contact 95 is isolated by the substrate 10 and the mesastructure 11 by the dielectric layer 49 and no semiconductor stressorlayer remains, it is possible to reduce a source-to-drain leak current,and to reduce parasitic junction capacitances between the semiconductorstressor layer and the substrate 11 and between the gate and thesource/drain. Further, the silicide layer 92 directly contacts theextension layer 26 and/or the channel semiconductor layer 25 and the S/Dcontact 95, which can reduce the contact resistance.

It will be understood that not all advantages have been necessarilydiscussed herein, no particular advantage is required for allembodiments or examples, and other embodiments or examples may offerdifferent advantages.

In accordance with one aspect of the present disclosure, in a method ofmanufacturing a semiconductor device, a fin structure in which firstsemiconductor layers and second semiconductor layers are alternatelystacked is formed, a sacrificial gate structure is formed over the finstructure, a source/drain region of the fin structure, which is notcovered by the sacrificial gate structure, is etched thereby forming asource/drain space, a stressor layer is formed in the source/drainspace, a metal gate structure including part of the second semiconductorlayer as channel regions is formed by a gate replacement process, afterthe metal gate structure is formed, the stressor layer is at leastpartially removed, and a source/drain contact comprising metal or ametallic material is formed in the source/drain space from which thestressor layer is at least partially removed. In one or more of theforegoing and following embodiments, the stressor layer includes asemiconductor material having a lattice constant different from thesecond semiconductor layers. In one or more of the foregoing andfollowing embodiments, the stressor layer is fully removed. In one ormore of the foregoing and following embodiments, after the stressorlayer is fully removed, the source/drain space is filled with adielectric material, and a dielectric layer is formed by partiallyremoving the dielectric material. The source/drain contact is formed onthe dielectric layer. In one or more of the foregoing and followingembodiments, after the stressor layer is fully removed and before thedielectric material is filled in the source/drain space, a firstextension semiconductor layer is formed on an end face of each of thesecond semiconductor layers. After the dielectric layer is formed, aside face of the first extension semiconductor layer is exposed in thesource/drain space. In one or more of the foregoing and followingembodiments, the first extension semiconductor layer includes dopant,and a doping concentration of the first extension semiconductor layer isgreater than a doping concentration of the second semiconductor layers.In one or more of the foregoing and following embodiments, after thedielectric layer is formed, a second extension semiconductor layer isformed on the side face of the first extension semiconductor layer, anda silicide layer is formed on the second extension semiconductor layeror by converting the second extension semiconductor layer into thesilicide layer. In one or more of the foregoing and followingembodiments, before the stressor layer is formed, inner spacers made ofa dielectric material are formed on end faces of the first semiconductorlayers. In one or more of the foregoing and following embodiments, apart of the dielectric material is formed on each of the inner spacersas an additional inner spacer.

In accordance with another aspect of the present disclosure, in a methodof manufacturing a semiconductor device, a fin structure in which firstsemiconductor layers and second semiconductor layers are alternatelystacked is formed, a sacrificial gate structure is formed over the finstructure, a source/drain region of the fin structure, which is notcovered by the sacrificial gate structure, is etched thereby forming asource/drain space, the first semiconductor layers are laterally etchedthrough the source/drain space, a first inner spacer made of adielectric material is formed on an end of each of the etched firstsemiconductor layers, a first extension semiconductor layer is formed onan end face of each of the second semiconductor layers in thesource/drain space, a stressor layer is formed in the source/drainspace, a first dielectric layer is formed over the stressor layer, agate space is formed by removing the sacrificial gate structure, thefirst semiconductor layers are removed in the gate space, therebyreleasing the second semiconductor layers as channel regions, a metalgate structure is formed around the second semiconductor layers, afterthe metal gate structure is formed, the stressor layer is at leastpartially removed, a dielectric liner layer is formed in thesource/drain space, an alloy layer is formed over the end face of eachof the second semiconductor layers, and a source/drain contactcomprising metal or a metallic material is formed in contact with thealloy layer. In one or more of the foregoing and following embodiments,a bottom of the source/drain contact is located closer to a substratethan a bottom face of one of the semiconductor layers closest to thesubstrate. In one or more of the foregoing and following embodiments,the source/drain contact is separated from the substrate by thedielectric liner layer. In one or more of the foregoing and followingembodiments, when the dielectric liner layer is formed, a second innerspacer is formed over the first inner spacer. In one or more of theforegoing and following embodiments, the alloy layer formed over an endface of one of the second semiconductor layers is separated by thesecond inner spacer from the alloy layer formed over an end face of anadjacent one of the second semiconductor layers. In one or more of theforegoing and following embodiments, when the alloy layer is formed, asecond extension semiconductor layer is formed on the first extensionsemiconductor layer, a metal layer is formed on the second extensionsemiconductor layer, and a thermal operation is performed to form thealloy layer from the second extension semiconductor layer and the metallayer.

In accordance with another aspect of the present disclosure, in a methodof manufacturing a semiconductor device, a fin structure in which firstsemiconductor layers and second semiconductor layers are alternatelystacked, is formed, a sacrificial gate structure is formed over the finstructure, a source/drain region of the fin structure, which is notcovered by the sacrificial gate structure, is etched thereby forming asource/drain space, a first dielectric stressor layer is formed in thesource/drain space, a second dielectric stressor layer having aninternal stress different from the first dielectric stressor layer isformed over the first dielectric stressor layer, a metal gate structureincluding part of the second semiconductor layer as channel regions isformed by a gate replacement process, after the metal gate structure isformed, the second dielectric stressor layer is removed, and asource/drain contact comprising metal or a metallic material is formedin the source/drain space from which the second dielectric stressorlayer is removed. In one or more of the foregoing and followingembodiments, the first and second dielectric stressor layers includehydrogenated silicon nitride, and a hydrogen amount of the seconddielectric stressor layer is different from a hydrogen amount of thefirst dielectric stressor layer. In one or more of the foregoing andfollowing embodiments, the source/drain contact is separated from asubstrate by the first dielectric stressor layer. In one or more of theforegoing and following embodiments, a bottom dielectric layer is formedat a bottom portion of the source/drain contact before the firstdielectric stressor layer is formed, and the source/drain contact isseparated from a substrate by the bottom dielectric stressor layer. Inone or more of the foregoing and following embodiments, an inner spaceris formed on an end of each of the first semiconductor layers, and thebottom dielectric layer and the inner spacers are made of a samematerial.

In accordance with another aspect of the present disclosure, asemiconductor device includes: a plurality of semiconductor bodiesdisposed and vertically arranged over a substrate, each of the pluralityof semiconductor bodies including a channel region and a source/drainregion; a gate dielectric layer disposed on and wrapping around thechannel region of each of the plurality of semiconductor bodies; a gateelectrode layer disposed on the gate dielectric layer and wrappingaround each channel region; an alloy layer disposed on an lateral endface of the source/drain region of each of the plurality ofsemiconductor bodies; and a source/drain contact comprising metal ormetallic material in contact with the alloy layer. In one or more of theforegoing and following embodiments, a bottom of the source/draincontact is located closer to the substrate than a bottom face of abottommost one of the plurality of semiconductor bodies. In one or moreof the foregoing and following embodiments, the semiconductor devicefurther includes a dielectric liner layer disposed between thesource/drain contact and the substrate. In one or more of the foregoingand following embodiments, the semiconductor device further includes afirst inner spacer disposed on a lateral end face of the gate dielectriclayer disposed between adjacent semiconductor bodies. In one or more ofthe foregoing and following embodiments, the semiconductor devicefurther includes a second inner spacer disposed on the first innerspacer and made of a same material as the dielectric liner layer. In oneor more of the foregoing and following embodiments, a dopantconcentration of the source/drain region gradually increases from thechannel region toward the source/drain contact. In one or more of theforegoing and following embodiments, the source/drain contact includesone or more layers of Ti, TiN, Ta, TaN, Co or W. In one or more of theforegoing and following embodiments, the channel region is coupled tothe source/drain contact without interposing a semiconductor crystalmaterial having a lattice constant different from the channel region.

In accordance with another aspect of the present disclosure, asemiconductor device includes: a substrate including a mesa structurehaving a bottom fin portion and a source/drain recess portion; aplurality of semiconductor bodies disposed and vertically arranged overthe bottom fin portion, each of the plurality of semiconductor bodiesincluding a channel region and a source/drain region; a gate structurewrapping around the channel region of each of the plurality ofsemiconductor bodies; a source/drain contact comprising metal ormetallic material; and a dielectric liner layer disposed between thesource/drain contact and the source/drain recess portion. In one or moreof the foregoing and following embodiments, a bottom part of thesource/drain contact is located at the source/drain recess portion. Inone or more of the foregoing and following embodiments, a bottom of thesource/drain contact is located closer to the substrate than a bottomface of a bottommost one of the plurality of semiconductor bodies. Inone or more of the foregoing and following embodiments, thesemiconductor device further includes a first inner spacer disposed on alateral end face of the gate structure disposed between adjacentsemiconductor bodies. In one or more of the foregoing and followingembodiments, the semiconductor device further includes a second innerspacer disposed on the first inner spacer and made of a same material asthe dielectric liner layer. In one or more of the foregoing andfollowing embodiments, the semiconductor device further includes asecond inner spacer disposed on the first inner spacer and made of adifferent material than the dielectric liner layer. In one or more ofthe foregoing and following embodiments, the dielectric liner layerincludes silicon nitride.

In accordance with another aspect of the present disclosure, asemiconductor device includes a first gate-all-around field effecttransistor (GAA FET), and a second GAA FET, Each of the first and secondGAA FET includes: a plurality of semiconductor bodies disposed andvertically arranged over a substrate, each of the plurality ofsemiconductor bodies including a channel region and a source/drainregion; and a gate structure wrapping around the channel region of eachof the plurality of semiconductor bodies. The first GAA FET includes afirst source contact and a common drain contact, comprising metal ormetallic material, and the second GAA FET includes the common draincontact and a second source contact comprising the metal or metallicmaterial, and a bottom of the common drain contact is located below abottommost one of the plurality of semiconductor bodies. In one or moreof the foregoing and following embodiments, the semiconductor devicefurther includes a dielectric liner layer disposed between the commondrain contact and the substrate. In one or more of the foregoing andfollowing embodiments, a bottom of the dielectric liner layer is locatedbelow a bottommost portion of the gate structure. In one or more of theforegoing and following embodiments, the semiconductor device furtherincludes a silicide layer disposed on a lateral end face of thesource/drain region of each of the plurality of semiconductor bodies,and the common drain contact is in contact with the alloy layer. In oneor more of the foregoing and following embodiments, the silicide layerdisposed on a lateral end face of the source/drain region of one of theplurality of semiconductor bodies is separated by a dielectric innerspacer from the silicide layer disposed on a lateral end face of thesource/drain region of an adjacent one of the plurality of semiconductorbodies.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising: forming a fin structure in which first semiconductor layersand second semiconductor layers are alternately stacked; forming asacrificial gate structure over the fin structure; etching asource/drain region of the fin structure, which is not covered by thesacrificial gate structure, thereby forming a source/drain space;forming a stressor layer in the source/drain space; forming a metal gatestructure including part of the second semiconductor layer as channelregions by a gate replacement process; after the metal gate structure isformed, at least partially removing the stressor layer; and forming asource/drain contact comprising metal or a metallic material in thesource/drain space from which the stressor layer is at least partiallyremoved.
 2. The method of claim 1, wherein the stressor layer includes asemiconductor material having a lattice constant different from thesecond semiconductor layers.
 3. The method of claim 2, wherein thestressor layer is fully removed.
 4. The method of claim 3, furthercomprising, after the stressor layer is fully removed: filling thesource/drain space with a dielectric material; and forming a dielectriclayer by partially removing the dielectric material, wherein thesource/drain contact is formed on the dielectric layer.
 5. The method ofclaim 4, further comprising, after the stressor layer is fully removedand before the dielectric material is filled in the source/drain space:forming a first extension semiconductor layer on an end face of each ofthe second semiconductor layers, wherein after the dielectric layer isformed, a side face of the first extension semiconductor layer isexposed in the source/drain space.
 6. The method of claim 5, wherein:the first extension semiconductor layer includes a dopant, and a dopingconcentration of the first extension semiconductor layer is greater thana doping concentration of the second semiconductor layers.
 7. The methodof claim 5, further comprising, after the dielectric layer is formed:forming a second extension semiconductor layer on the side face of thefirst extension semiconductor layer; and forming a silicide layer on thesecond extension semiconductor layer or by converting the secondextension semiconductor layer into a silicide layer.
 8. The method ofclaim 4, further comprising, before the stressor layer is formed:forming inner spacers made of a dielectric material on end faces of thefirst semiconductor layers.
 9. The method of claim 8, wherein a part ofthe dielectric material is formed on each of the inner spacers as anadditional inner spacer.
 10. A method of manufacturing a semiconductordevice, comprising: forming a fin structure in which first semiconductorlayers and second semiconductor layers are alternately stacked; forminga sacrificial gate structure over the fin structure; etching asource/drain region of the fin structure, which is not covered by thesacrificial gate structure, thereby forming a source/drain space;laterally etching the first semiconductor layers through thesource/drain space; forming a first inner spacer made of a dielectricmaterial on an end of each of the etched first semiconductor layers;forming a first extension semiconductor layer on an end face of each ofthe second semiconductor layers in the source/drain space; forming astressor layer in the source/drain space; forming a first dielectriclayer over the stressor layer; forming a gate space by removing thesacrificial gate structure; removing the first semiconductor layers inthe gate space, thereby releasing the second semiconductor layers aschannel regions; forming a metal gate structure around the secondsemiconductor layers; after the metal gate structure is formed, at leastpartially removing the stressor layer; forming a dielectric liner layerin the source/drain space; forming an alloy layer over the end face ofeach of the second semiconductor layers; and forming a source/draincontact comprising metal or a metallic material in contact with thealloy layer.
 11. The method of claim 10, wherein a bottom of thesource/drain contact is located closer to a substrate than a bottom faceof one of the semiconductor layers closest to the substrate.
 12. Themethod of claim 11, wherein the source/drain contact is separated fromthe substrate by the dielectric liner layer.
 13. The method of claim 10,wherein the forming the dielectric liner layer comprises forming asecond inner spacer over the first inner spacer.
 14. The method of claim13, wherein the alloy layer formed over an end face of one of the secondsemiconductor layers is separated by the second inner spacer from thealloy layer formed over an end face of an adjacent one of the secondsemiconductor layers.
 15. The method of claim 10, wherein the formingthe alloy layer comprises: forming a second extension semiconductorlayer on the first extension semiconductor layer; forming a metal layeron the second extension semiconductor layer; and performing a thermaloperation to form the alloy layer from the second extensionsemiconductor layer and the metal layer.
 16. A semiconductor devicecomprising: a first gate-all-around field effect transistor (GAA FET);and a second GAA FET, wherein: each of the first and second GAA FETincludes: a plurality of semiconductor bodies disposed and verticallyarranged over a substrate, each of the plurality of semiconductor bodiesincluding a channel region and a source/drain region; and a gatestructure wrapping around the channel region of each of the plurality ofsemiconductor bodies, the first GAA FET includes a first source contactand a common drain contact, comprising metal or metallic material, andthe second GAA FET includes the common drain contact and a second sourcecontact comprising the metal or metallic material, and a bottom of thecommon drain contact is located below a bottommost one of the pluralityof semiconductor bodies.
 17. The semiconductor device of claim 16,further comprising a dielectric liner layer disposed between the commondrain contact and the substrate.
 18. The semiconductor device of claim17, wherein a bottom of the dielectric liner layer is located below abottommost portion of the gate structure.
 19. The semiconductor deviceof claim 16, further comprising a silicide layer disposed on a lateralend face of the source/drain region of each of the plurality ofsemiconductor bodies, the common drain contact is in contact with thealloy layer.
 20. The semiconductor device of claim 19, wherein thesilicide layer disposed on a lateral end face of the source/drain regionof one of the plurality of semiconductor bodies is separated by adielectric inner spacer from the silicide layer disposed on a lateralend face of the source/drain region of an adjacent one of the pluralityof semiconductor bodies.